The present invention relates to an abrasive composition generally employed for polishing a semiconductor device and to a method for producing the semiconductor device using the composition.
Recently, as a method for isolating elements in a semiconductor device, a shallow trench isolation method which enables production of semiconductor devices of high package density has become of interest. This method is a technique employed instead of a conventional local oxidation of silicon (LOCOS). Specifically, trench isolation is a method of interest in which a silicon nitride film is formed on a silicon substrate; a shallow trench is formed; an oxide film is formed on the nitride film; and the surface is planarized through CMP by use of the silicon nitride film as a stopper. The trench isolation method, being capable of advantageously providing a wide effective element area, is quite a promising technique for producing LSIs of high package-density.
When LSIs of high package-density are produced through this method in which a silicon nitride film is provided underneath the oxide film to be polished and polishing is performed by use of the silicon nitride film as a stopper, a uniform device surface can be obtained by evenly polishing off the removal amount of the surface to be planarized. Polishing can be terminated in a well-controlled manner at a point at which a predetermined removal amount has reached.
Regarding abrasive compositions suitable for such a method, Japanese Patent Application Laid-Open (kokai) No. 9-194823 discloses an abrasive composition containing abrasive particles such as silicon nitride, silicon carbide, and graphite, and Japanese Patent Application Laid-Open (kokai) No. 9-208933 discloses an abrasive composition containing silicon nitride powder and an acid such as gluconic acid.
Although these abrasive compositions provide a high polishing rate due to high-hardness abrasives incorporated therein, many scratches are formed on the polished surface by the abrasives, thereby cause problems such as deterioration of the performance of LSIs.
In addition, since the polishing index of oxide film (silicon dioxide film is typically used) with respect to silicon nitride film serving as a stopper (typically, the index is represented by xe2x80x9cselectivityxe2x80x9d)xe2x80x94in other words, the rate of polishing oxide film divided by the rate of polishing silicon nitride filmxe2x80x94attained through a conventional technique is unsatisfactory, there is demand for further elevating the index.
In view of the foregoing, the present inventors previously disclosed, in International Patent Publication WO 99/43761, an abrasive composition for polishing a semiconductor device comprising water, cerium oxide, a water-soluble organic compound having at least one functional group selected from among xe2x80x94COOH, xe2x80x94COOMX groups (MX represents an atom or a functional group capable of forming a salt through substitution by an H atom), xe2x80x94SO3H, and xe2x80x94SO3MY groups (MY represents an atom or a functional group capable of forming a salt through substitution by an H atom), the abrasive composition further containing an optional chelating agent. The inventors also proposed a method for forming an element through shallow trench isolation by use of the abrasive composition.
When such an abrasive composition as disclosed in the above patent publication is used, a high selectivity can be attained and scratches on the wafer surface can be advantageously reduced. However, washing performance of the polished wafer surface is unsatisfactorily.
U.S. Pat. No. 5,738,800 discloses a composition containing water, abrasive particles, a surfactant, and a compound which can form a complex with silicon oxide or silicon nitride, and a method for forming a shallow trench isolation structure by use of the composition. The patent publication clearly specifies that a high selectivity can be attained only when the surfactant is added and that addition of the surfactant is essential. Specifically, the employed abrasive composition contains a fluorine-containing surfactant in an amount of approximately 0.1-0.5%. However, since most surfactants exhibit a strong surface activation effect and foam-generating property, an abrasive composition containing such a surfactant is not always suited for polishing a semiconductor device.
Japanese Patent Application Laid-Open (kokai) No. 10-163140 discloses a polishing method for planarizing the semiconductor device surface including a main polishing step in which polishing is performed by use of a first polishing liquid, and a finish polishing step making use of a chelating agent.
However, the two-step polishing method attains low efficiency, leading to a problematic low production yield.
Japanese Patent Application Laid-Open (kokai) No. 7-70553 discloses a polishing liquid for polishing an aluminum-containing substrate, containing a chelating agent which can form a complex with aluminum. However, since the technique disclosed in that publication is intended for application to polishing a glass substrate or a similar substrate, the performance required of the composition is completely different from that required for forming a shallow trench isolation structure according to the present invention.
As described above, in order to form a shallow trench isolation structure, there is a strong demand for an abrasive composition attaining a high selectivity, providing few scratches on the polished surface, and readily removing abrasive particles through washing.
An object of the present invention is to provide an abrasive composition for polishing a semiconductor device, which composition can solve the aforementioned drawbacks and problems. Another object of the present invention is to provide a method for producing a semiconductor device such that the aforementioned problems can be solved.
The present inventors have conducted extensive studies in order to solve the aforementioned problems, and as a result have accomplished the present invention. Accordingly, the present invention provides the following:
(1) an abrasive composition for polishing a semiconductor device comprising water, microparticles of an abrasive, and a chelating agent, characterized in that the abrasive is cerium oxide; the microparticles of cerium oxide have an average particle size of 0.01-1.0 xcexcm; and, when silicon nitride film and silicon oxide film, separately formed on a silicon substrate through CVD, are polished separately under identical conditions, the ratio of the rate of polishing the silicon nitride film to the rate of polishing the silicon oxide film is 10 or more;
(2) an abrasive composition for polishing a semiconductor device as described in (1), wherein the abrasive includes cerium oxide microparticles and additional microparticles for polishing;
(3) an abrasive composition for polishing a semiconductor device as described in (2), wherein the additional abrasive microparticles are formed of at least one species selected from the group consisting of aluminum oxide, zirconium oxide, silicon dioxide, titanium dioxide, manganese dioxide, dimanganese trioxide, chromium oxide, iron oxide, tin oxide, zinc oxide, alumina-magnesia spinel, mullite, zircon, aluminum hydroxide, calcium hydroxide, magnesium hydroxide, silicon nitride, titanium nitride, boron nitride, silicon carbide, titanium carbide, and diamond;
(4) an abrasive composition for polishing a semiconductor device as described in (1), wherein the concentration of said cerium oxide is 0.1-10 mass % and the chelating agent is added at a mass ratio of 0.01-10 based on the mass of said cerium oxide;
(5) an abrasive composition for polishing a semiconductor device as described in (2), wherein the total concentration of said cerium oxide microparticles and the additional microparticles for polishing is 0.1-10 mass % and the chelating agent is added at a mass ratio of 0.01-10 based on the mass of the sum of microparticles;
(6) an abrasive composition for polishing a semiconductor device as described in (1) or (2), wherein the chelating agent is at least one compound selected from the group consisting of ethylenediaminetetraacetic acid (EDTA), cyclohexanediaminetetraacetic acid (CyDTA), nitrilotriacetic acid (NTA), hydroxyethylethylenediaminetriacetic acid (HEDTA), diethylenetriaminepentaacetic acid (DTPA), triethylenetetraminehexaacetic acid (TTHA), L-glutaminediacetic acid (GLDA), aminotri(methylenephosphonic acid), 1-hydroxyethylidene-1,1-diphosphonic acid, ethylenediaminetetra(methylenephosphonic acid), diethylenetriaminepenta(methylenephosphonic acid), xcex2-alaninediacetic acid (ADA), xcex1-alaninediacetic acid (xcex1-ADA), asparaginediacetic acid (ASDA), ethylenediaminedisuccinic acid (EDDS), iminodiacetic acid (IDA), hydroxyethyliminodiacetic acid (HEIDA), and 1,3-propanediaminetetraacetic acid (1,3-PDTA), or a salt thereof;
(7) an abrasive composition for polishing a semiconductor device as described in (1), further comprising a dispersant having a concentration of 0.08 mass % or less;
(8) an abrasive composition for polishing a semiconductor device as described in (1), further comprising a dispersant, the dispersant containing a poly(acrylic acid) moiety or a poly(methacrylic acid) moiety, and the concentration of the dispersant being 0.08 mass % or less;
(9) an abrasive composition for polishing a semiconductor device as described in (1) or (7), wherein the abrasive composition for polishing a semiconductor device contains, as an impurity other than abrasive material microparticles components, at least one element selected from the group consisting of Mg, Al, K, Ca, Fe, Ni, Cu, Mn, Th, and U at a concentration, for each element, of 30 ppm or less;
(10) cerium oxide microparticles for use in an abrasive composition for polishing a semiconductor device as described in (1) or (7), characterized by having a purity of 99.9 mass % or more and containing, as an impurity, at least one element selected from the group consisting of Mg, Al, K, Ca, Fe, Ni, Cu, Mn, Th, and U at a concentration of 30 ppm or less;
(11) a method for producing a semiconductor device comprising forming a silicon nitride film on a semiconductor substrate; subsequently, selectively removing a part of the silicon nitride film, to thereby develop the semiconductor substrate; subsequently, etching the semiconductor substrate by use of the silicon nitride film as a mask, to thereby form a trench; depositing a silicon oxide film on the silicon nitride film and on the semiconductor substrate, to thereby completely bury the trench with the silicon oxide film; and planarization-polishing the silicon oxide film by use of the silicon nitride film as a stopper, to thereby selectively leave said silicon oxide in the trench, wherein the planarization-polishing is performed by use of an abrasive composition for polishing a semiconductor device as recited in (1) or (2); and
(12) a semiconductor substrate having an element-isolated structure produced through the following steps: forming a silicon nitride film on a semiconductor substrate; subsequently, selectively removing a part of the silicon nitride film, to thereby develop the semiconductor substrate; subsequently, etching the semiconductor substrate by use of the silicon nitride film as a mask, to thereby form a trench; depositing a silicon oxide film on the silicon nitride film and on the semiconductor substrate, to thereby completely bury the trench with the silicon oxide film; and planarization-polishing the silicon oxide film by use of the silicon nitride film as a stopper, to thereby selectively leave said silicon oxide in the trench, wherein the planarization-polishing is performed by use of an abrasive composition for polishing a semiconductor device as recited in (1) or (2).
According to the method of the present invention, scratches on the polished surface can be reduced, and a shallow trench isolation structure can suitably be formed in a well-controlled manner. In addition, abrasive particles can readily be removed from the polished wafer through washing.